Er Ajith Ravindran

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Er Ajith Ravindran

Er Ajith Ravindran

Designation: Assistant Professor 
Education:  M Tech, Pursuing PhD
Professional Experience
Teaching  : 7.9 years

Specialization
UG : Electronics & Communication Engineering

PG  :VLSI & Embedded Systems

Publications

  • Arunima C V , Gowry Nair S , Krishna Gadha S Kumar , Santy Sajan, Ajith Ravindran., A Retrospective Study on Crop Dependent Drip Irrigation System, International Research Journal of Engineering and Technology, Volume: 07 Issue: 07 ,July 2020
  • Ravindran, A., Nesamani, F.P. and Nirmal, D., 2018, December. A Study on the use of Spectroscopic Techniques to Identify Food Adulteration. In 2018 International Conference on Circuits and Systems in Digital Enterprise Technology (ICCSDET) (pp. 1-6). IEEE.
  • James, R.M. and Ravindran, A., 2018, March. Review of Full Adder Performance Analysis Using Kogge Stone Adder and Magnetic Tunnel Junction. In 2018 4th International Conference on Devices, Circuits and Systems (ICDCS) (pp. 84-90). IEEE.
  • Shilpa, K.S, Ravindran, A. and Saranya, P.M., Design of Standard Cell ASIC’S Using Self Gated Resonant Clocked Flip Flop, ICTACT Journal on Microelectronics, July 2017, Volume: 03, Issue: 02.
  • Jose, J., Ravindran, A. and Nair, K.K., A Highly Sensitive Heterojunction Photodetector for UV Application, International Journal of Engineering Research & Technology (IJERT),ISSN: 2278-0181 IJERTV5IS090580 Vol. 5 Issue 09, September-2016
  • Nair, K.K., Jose, J. and Ravindran, A., 2016. Analysis of temperature dependent parameters on solar cell efficiency using MATLAB. International Journal of Engineering Development and Research, 4, pp.536-541.
  • Varghese, A., Praveen, C.S., Mani, A.P. and Ravindran, A., In GaAs/GaAsSb Heterojunction TFET, IJCA Proceedings on International Conference on Emerging Trends in Technology and Applied Science.
  • Praveen, C.S., Ravindran, A., John, S.K. and Abe, S., 2015. Gate Engineering of Double Gate In0. 53Ga0. 47As Tunnel FET. ICTACT Journal on Microelectronics, 1, p.91.
  • Ravindran, A., George, A., Praveen, C.S. and Kuruvilla, N., 2017. Gate All Around Nanowire TFET with High ON/OFF Current Ratio. Materials Today: Proceedings, 4(9), pp.10637-10642.
  • Sudheer, A. and Ravindran, A., 2015. Design and implementation of embedded logic flip-flop for low power applications. Procedia Computer Science, 46, pp.1393-1400.
  • Joseph, T.S. and Ravindran, A., 2014, July. Implementation of non-volatile 4× 4 4T1D DRAM cell in 0.18 μm technology. In 2014 International Conference on Control, Instrumentation, Communication and Computational Technologies (ICCICCT) (pp. 435-439). IEEE.
  • Ravindran, A., 2014, Design & Implementation of Embedded Logic Flip-Flop in 180nm Technology. International Journal of Engineering Research, 3(6).
  • Thomas, A., Jose, S.H., Prasad, A. and Ravindran, A., 2014, Speed control of a DC motor using fractional order proportional derivative (FOPD) control. International Journal of Engineering Research and Technology, 3(1), pp.3460-3464.
  • A 1.5V Area Efficient Asynchronous Adder using MODL and Double Pass Transistor Logic – IJSER
  • Speed Control of a DC Motor Using Fractional order Proportional Derivative (FOPD) Control – IJERT
  • Design & Implementation of Embedded Logic Flip Flop in 180nm Technology- IJERT
  • Design and Implementation of Embedded Logic Flip-Flop for Low Power Applications – Elsevier Procedia Computer Science
  • Analysis of GAA Tunnel FET using MATLAB – IJCA
  • Comparative study on Silicon and Germanium Doping-less Tunnel FET – IJSTE
  • Impact of Doping in Gate All Around Nanowire TFET – IJAREEIE
  • Gate Engineering of Double Gate In0.53Ga0.47As Tunnel FET – ICTACT Journal on Microelectronics
  • InGaAs/ GaAsSb Heterojunction TFET – IJCA
  • A Review on Non-Destructive Techniques for Evaluating Quality of Fruits – IJERT
  • Analysis of Temperature Dependent Parameters on Solar Cell Efficiency using MATLAB – IJEDR
  • Analysis of Temperature Effect on MOSFET Parameter using MATLAB – IJEDR
  • A Highly Sensitive Heterojunction Photodetector for UV Application –  IJERT
  • A review on ZnO Heterojunction Photodetector for UV Application – ICTACT Journal on Microelectronics
  • Area Efficient Quad Bit PTL Adder – National Conference on VLSI and Embedded Systems Technology and Advancements, VESTA2012
  • 1.5v, .18u Area Efficient 32 Bit Adder Using 4T XOR & Modified Manchester Carry Chain – 12th International Conf. on Intelligent System Design and Applications (ISDA)
  • A 1.5V Area Efficient Asynchronous Adder using MODL and Double Pass Transistor Logic – International Conference on Global Innovations and Technology ( ICGITS) 
  • Comparative Analysis of Flip-Flops for High Performance Systems in .18um Technology. – National Conference on Recent trends in Electronics World,  TKMIT, Kollam.
  • Performance Comparison of DRAM cells and Extending non – Volatile memory concept in 0.18um technology. – National Conference on New trends in Electronics, Computing and Communication (NTECC-14)
  • Implementation and Performance Analysis of Universal Gates using Tunneling Field Effect Transistor – International Conference on Engineering and Material Sciences-ICEMS-2016
  • Detection and Analysis of Chemical Compositions using Hyperspectral Imaging with the help of Spectral Signatures – National Conference on Novel and Challenging Issues and Recent Innovations in Engineering and Information Sciences
  • Dual Metal Gate all around nanowire TFET with Hetero Dielectric: A TCAD study – IEEE SSCS Sponsored 4th conference of Solid state circuits

Participations

Workshop/Seminars Attended

  • AICTE Training And Learning (ATAL) Academy Online FDP on “Computer Science & Biology ” from 2020-8-24 to 2020-8-28 at Amal Jyothi College of Engineering.
  • MathWorks training on Machine Learning with MATLAB, Control System Design with MATLAB and Simulink, and Embedded Coder
  • Workshop on “Design, Development and launching of MOOC” conducted by Bennett University, Greater Noida, India
  • NPTEL-AICTE FDP on the course “Infra Red Spectroscopy for Pollution Monitoring”
  • Additional training in industry tools in connection with Tailor Made Course in IC Design
  • Short Term course on “Microelectronics: from Fundamentals to Devices” by IIT Madrass
  • National workshop on Advanced Nano scale device design using TCAD
  • IETE sponsored FDP on Embedded Design Using ARM & ARDUINO
  • INUP hands on training on Solar Cell Fabrication by IITB
  • IETE Sponsored National Level Faculty Development Programme on CAD Tools in VLSI & Communication
  • INUP workshop on Nanofabrication technologies

Events Organized 

  • IIRS Outreach Program of ISRO – Coordinator
  • Srishti 2019- National level Project exhibition and competition
  • Workshop on Modeling and Simulation o MEMS Using Intellisuite Software
  • IEEE SSCS Distinguished Lecture by Dr. Yong Ping Xu
  • IEEE SSCS Sponsored Tailor Made Course in IC Design
  • Third Conference on Solid State Circuits funded by IEEE SSCS
  • Second Conference on Solid State Circuits funded by IEEE SSCS
  • Distinguished Lecture by Dr. Jacob Baker for IEEE members under IEEE Kerala Section
  • Three day Workshop & Conference on Solid State Circuits funded by IEEE SSCS
  • Workshop on Xilinx Based Digital design for IEEE Members
  • Two day STTP on “XILINX FPGA Based System Design” (Sponsored by TEQUIP Phase II)

Memberships

  • IEEE Senior Member
  • IEEE SSCS Professional Member
  • IE(I) Associate Member

R & D Projects

  • InGaAs/GaAsSb Heterojunction TFET for Realization of Energy Efficient Complementary Logic Circuit (Project ID : PG2015030 ) – Co-investigator, IE(I) Student Project
  • Analysis of gate all around tunnel field effect transistor using TCAD (15/SPS55/ 2015/ KSCSTE ) – Co-investigator, KSCSTE Student Project
  • Analysis of dopingless heterojunction tunnel field effect transistor using TCAD(16/SPS55/ 2015/ KSCSTE ) – Co-investigator, KSCSTE Student Project
  • Handheld Device for the Detecion of Artificially Ripened Fruits and Chemically Treated Vegetables – Co-investigator, APJ Youcth Challenge Programme, KSCSTE.

Achievements

  • Best Paper Award – National Conference on VLSI and Embedded Systems Technology and Advancements,VESTA2012.

  • Received IEEE SSCS Extra chapter Subsidy of $4389 in the year 2013

  • Received IEEE SSCS Extra chapter Subsidy of $3250 in the year 2014

  • Received IEEE SSCS Extra chapter Subsidy of $3500 in the year 2016

Contact Details
Mobile : +91 8606432966
Email : ajith.ravindran@saintgits.org

Quick Contact

SAINTGITS COLLEGE OF ENGINEERING

Kottukulam Hills, Pathamuttom
PO Kottayam, Pin – 686532, Kerala

Tel: +91 481 2430349, 2436169, 2436170

Email: mail@saintgits.org

For Admission please contact:
Anju Anna Jacob
Admissions Officer
+91 9895903278, +91 8129702585
anjukakkad@saintgits.org

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