Er Ajith Ravindran

LATEST UPDATES

120 Students of Saintgits College of Engineering and 22 Students of Saintgits College of Applied Sciences placed in Infosys
Department of Corporate Economics will hold a National Seminar on “Economics Slowdown of India” in December 2019.
Congratulations Saintgits Chess Women’s Team – KTU C Zone Intercollegiate Chess Tournament Champions
Saintgits wins the prestigious IDA – STEM Award for Community Development.
National Seminar by Business Administration Department on the theme “Unleash Entrepreneurship in Trade & Commerce”  will be held on December 11, 2019.
Ms. Angel Baby and Ms. Gayathri R. from final year BCA of Saintgits College of Applied Sciences bagged the first placement offers in the new campus recruitment season. Both of them placed as Associate Analyst in Deloitte.
Er Ajith Ravindran

Er Ajith Ravindran

Designation: Asst. Professor 
Education:  M Tech, Pursuing PhD
Professional Experience
Teaching  : 5.5 years

 

Specialization
UG : Electronics & Communication Engineering
PG  :VLSI & Embedded Systems

 

Publications

  • A 1.5V Area Efficient Asynchronous Adder using MODL and Double Pass Transistor Logic – IJSER
  • Speed Control of a DC Motor Using Fractional order Proportional Derivative (FOPD) Control – IJERT
  • Design & Implementation of Embedded Logic Flip Flop in 180nm Technology- IJERT
  • Design and Implementation of Embedded Logic Flip-Flop for Low Power Applications – Elsevier Procedia Computer Science
  • Analysis of GAA Tunnel FET using MATLAB – IJCA
  • Comparative study on Silicon and Germanium Doping-less Tunnel FET – IJSTE
  • Impact of Doping in Gate All Around Nanowire TFET – IJAREEIE
  • Gate Engineering of Double Gate In0.53Ga0.47As Tunnel FET – ICTACT Journal on Microelectronics
  • InGaAs/ GaAsSb Heterojunction TFET – IJCA
  • A Review on Non-Destructive Techniques for Evaluating Quality of Fruits – IJERT
  • Analysis of Temperature Dependent Parameters on Solar Cell Efficiency using MATLAB – IJEDR
  • Analysis of Temperature Effect on MOSFET Parameter using MATLAB – IJEDR
  • A Highly Sensitive Heterojunction Photodetector for UV Application –  IJERT
  • A review on ZnO Heterojunction Photodetector for UV Application – ICTACT Journal on Microelectronics
  • Area Efficient Quad Bit PTL Adder – National Conference on VLSI and Embedded Systems Technology and Advancements, VESTA2012
  • 1.5v, .18u Area Efficient 32 Bit Adder Using 4T XOR & Modified Manchester Carry Chain – 12th International Conf. on Intelligent System Design and Applications (ISDA)
  • A 1.5V Area Efficient Asynchronous Adder using MODL and Double Pass Transistor Logic – International Conference on Global Innovations and Technology ( ICGITS) 
  • Comparative Analysis of Flip-Flops for High Performance Systems in .18um Technology. – National Conference on Recent trends in Electronics World,  TKMIT, Kollam.
  • Performance Comparison of DRAM cells and Extending non – Volatile memory concept in 0.18um technology. – National Conference on New trends in Electronics, Computing and Communication (NTECC-14)
  • Implementation and Performance Analysis of Universal Gates using Tunneling Field Effect Transistor – International Conference on Engineering and Material Sciences-ICEMS-2016
  • Detection and Analysis of Chemical Compositions using Hyperspectral Imaging with the help of Spectral Signatures – National Conference on Novel and Challenging Issues and Recent Innovations in Engineering and Information Sciences
  • Dual Metal Gate all around nanowire TFET with Hetero Dielectric: A TCAD study – IEEE SSCS SPonsored 4th conference of Solid state circuits

Memberships

  • IEEE Professional Member
  • IEEE SSCS Professional Member
  • IE(I) Associate Member

R & D Projects

  • InGaAs/GaAsSb Heterojunction TFET for Realization of Energy Efficient Complementary Logic Circuit (Project ID : PG2015030 ) – Co-investigator, IE(I) Student Project
  • Analysis of gate all around tunnel field effect transistor using TCAD (15/SPS55/ 2015/ KSCSTE ) – Co-investigator, KSCSTE Student Project
  • Analysis of dopingless heterojunction tunnel field effect transistor using TCAD(16/SPS55/ 2015/ KSCSTE ) – Co-investigator, KSCSTE Student Project
  • Handheld Device for the Detecion of Artificially Ripened Fruits and Chemically Treated Vegetables – Co-investigator, APJ Youcth Challenge Programme, KSCSTE.

Achievements

  • Best Paper Award – National Conference on VLSI and Embedded Systems Technology and Advancements,VESTA2012.

  • Received IEEE SSCS Extra chapter Subsidy of $4389 in the year 2013

  • Received IEEE SSCS Extra chapter Subsidy of $3250 in the year 2014

  • Received IEEE SSCS Extra chapter Subsidy of $3500 in the year 2016

Contact Details
Mobile : +91 8606432966
Email : ajith.ravindran@saintgits.org

Quick Contact

SAINTGITS COLLEGE OF ENGINEERING

Kottukulam Hills, Pathamuttom
PO Kottayam, Pin – 686532, Kerala

Tel: +91 481 2430349, 2436169, 2436170

Email: mail@saintgits.org

For Admission please contact:
Anju Anna Jacob
Admissions Officer
+91 9895903278, +91 8129702585
anjukakkad@saintgits.org

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