Er Aravindhan A

Er Aravindhan A
Er Aravindhan A

Er Aravindhan A

Designation : Asst Professor Sr
Education : M.Tech, (Ph. D.,)
Professional Experience 
Teaching : 10 Yrs

Research : 3 Yrs
Industry : 3.3 Yrs


Specialization :

UG : Electrical and Electronics Engineering
PG : VLSI Design
Ph.D : Network on Chip


International Journal Paper:

  • Aravindhan. A, Shalini S, Lakshminarayanan. G, “Cluster Based Application Mapping Strategy for 2D NoC” Journal of Procedia Technology, PP. 505-512, Vol.25, Elsevier publications, 2016, DOI:10.1016/j.protcy.2016.08.138
  • Shalini S, Aravindhan. A, Lakshminarayanan. G, “A Case Study on Cluster Based Power Aware Mapping Strategy for 2D NoC” ICTCAT Journal of Microelectronics, PP. 315-322, Vol.2 (4), 2017, DOI:10.21917/ijme.2017.0055
  • Meenu Anna George, Aravindhan. A, Lakshminarayanan. G, “Design of Five Port Priority Based Router with Port Selection logic for NoC” ICTCAT Journal of Microelectronics, PP. 293-299, Vol.2 (4), 2017, DOI:10.21917/ijme.2017.0051
  • Thara Sebastian, A. Aravindhan, “Case Study on Explicit and Implicit Pulsed Flip Flop with Conditional Pulse Enhancement Scheme”, ICTACT Journal on Microelectronics (IJME), Vol. 3(1), pp 120 – 123, 2015, DOI:10.21917/ijme.2015.0020
  • Thara Sebastian, A. Aravindhan, “Power Efficient Dual Dynamic Node Flip Flop with Embedded Logic by Adopting PCS”, International Journal of Science Technology & Engineering, Vol. 2(4), 2015
  • P.Sivakumar, A. Aravindhan, P. Subbaraj, “Multithread Hybrid Genetic Algorithm for VLSI Physical Design Specific to Placement Problem”, International Journal of Computer Information Technology and Engineering, Vol. 3(1), pp 77 – 80, 2009

International Conference Proceedings:

  • A. Aravindhan Alagarsamy, Lakshminarayanan G, “ SAT: A New Application Mapping Method for Power Optimization in 2D-NoC”, 20th International Symposium on VLSI Design and Test (VDAT), IIT, Guwahati, 2016
  • A. Aravindhan, S Anand, PS Godwin Anand, “An Analogues Computation on Hybrid Genetic Algorithm for VLSI Physical Design Specific to Placement Problem”, International Conference on VLSI, Communication and Instrumentation, 2011
  • A. Aravindhan, PS Godwin Anand, Singana Sudhaker Reddy, “On Chip Communication Network Design for Digital Camera”, International Journal of Computer Applications, International Conference on VLSI, Communication and Instrumentation, 2011

National Conference Proceedings:

  • A. Aravindhan, S Anand, P Sivakumar, “Multi – Warned Genetic Algorithm for VLSI Physical Design Specific to Placement Problem”, National Conference on Electronic Systemic Informatics and Cinematic, 2009
  • Saranya Janarthanan, Shonima Shaji, A. Aravindhan, “An Effective Macro Cell Placement with Overlap Removal by Adopting Evolutionary Algorithm ”, National Conference on Recent Trends in Information and Communication Engineering, 2013


Participation in Workshops:

  • Five days workshop on “Mixed Signal & RF IC Design”, Sponsored by NMEICT, Indian Institute of Technology (IIT), Kharagpur from 19th Sep 2016 to 23rd Sep 2016
  • Five days workshop on “Research Trends in Semiconductor Device Modeling and Fabrication”, Sponsored by TEQUIP, College of Engineering, Cherthala from 08th Dec. 2014 to 12th Dec 2014
  • One week Faculty Development Program (FDP) on “CAD Tools in VLSI & Communication Systems”, Sponsored by IETE, Saintgits College of Engineering from 28th Nov. 2014 to 05th Dec. 2015
  • Two week ISTE STTP on “ Signals & Systems”, Organized by Indian Institute of Technology, Kharagpur, from 02nd Jan. 2014 to 12th Jan. 2014
  • Four days workshop on “Outcome Based Accreditation Process”, Sponsored by NBA, Saintgits College of Engineering, from 13th Sep. 2013 (Phase I) & 03rd Oct. 2013 to 05th Oct 2013 (Phase II)
  • One day workshop on “Project Design and Proposal Writing”, Organized by IUCDS, Mahatma Gandhi University, Kottayam, 10th May 2013
  • One day workshop on “MATLAB & Simulink for Engineering Education”, Organized by MathWorks, Bangalore, 25th Feb. 2013
  • Two days workshop on “LaTex and Engineering”, Organized by Internal Quality Assurance Cell (IQAC), Saintgits College of Engineering from 10th Jan. 2013 to 11th Jan. 2013
  • Five days workshop on “Continuing Engineering Education”, Sponsored by IEEE Kochi Section, St. Joseph College of Engineering. & Technology from 08th Oct. 2012 to 12th Oct. 2012
  • Two days Faculty Development Program (FDP) on “Digital Logic Design using HDL”, Organized by FACTS-ELCi, Saintgits College of Engineering from 21st Dec. 2010 to 22nd Dec. 2010
  • Two days workshop on “Advanced Learning & Training – Mission 10X”, Organized by WIPRO Technologies from 22nd Oct. 2010 to 23rd Oct. 2010
  • One week workshop on “High Impact Teaching Skills – Mission 10X”, Organized by WIPRO Technologies from 26th Feb. 2010 to 03rd Mar. 2010
  • One week workshop on “Embedded System Design using PIC Microcontroller”, Organized by Rhydo Technologies, Bangalore from 07th Dec. 2009 to 12th Dec. 2009
  • One week workshop on “Programmable Logic Controller”, Sponsored by ISA, Saintgits College of Engineering from 13th Dec. 2009 to 18th Dec. 2009
  • One week Quality Improvement Program (QIP) on “ Student Psychology Vs Teaching Methodology”, Organized by NITTTR, Chennai from 02nd Nov. 2009 to 07th Nov. 2009
  • Five days STTP on “Research Trends in Embedded System & Signal Processing”, Sponsored by ISTE, Saintgits College of Engineering from 28th Oct. 2009 to 01st Nov. 2009
  • One week workshop on “Embedded System & VLSI Design in Robotics Application”, Organized by I2IT Center of Excellence for Robotics, International Institute of Information Technology, Pune, Maharashtra from 18th Feb. 2008 to 24th Feb 2008
  • Two days workshop on “Introduction to Mechatronics”, Sponsored by ISTE, PSNA College of Engineering & Technology from 16th Feb. 2007 to 17th Feb. 2007


  • Institution of Engineers (India) – IEI
  • Institution of Electrical and Electronics Engineers – IEEE
  • Indian Society of Technical Education – ISTE
  • International Association of Engineering – IAEng
  • International Association of Engineers & Scientists – IAEST

Research Interest

  • VLSI Physical Design Issues
  • Low Power VLSI Design
  • Network on Chip (NoC)
  • Micro Electro Mechanical System (MEMS)
  • Evolutionary Algorithm



  • Reviewer of Journal of The Institution of Engineers (India): Series B, Springer Publication House
  • Reviewer of Journal of Microelectronics, Elsevier, Science Direct Publication House

Professional Contributions:

  • Workshop Co-ordinator, Six Days National Level Workshop on “CMOS, Mixed Signal and RF VLSI Design”, Sponsored by NMEICT, IIT, Kharagpur, Saintgits College of Engineering, from 30th Jan. 2017 to 04th Feb. 2017
  • Organized Head, One day talk on “E – Waste Management”, 15th September 2015
  • Organizing member, Three Days National Level Workshop on “Signal Processing in VLSI Design”, Sponsored by Kerala State Center of Science and Technology (KSCSTE), Saintgits College of Engineering, from 28th Aug. 2015 to 30th Aug. 2015
  • Advisor, Institution of Engineers (India) Students’ Chapter, Saintgits College of Engineering from June 2015
  • Teaching Assistant, ISTE STTP on “Introduction to Design of Algorithms”, Organized by Indian Institute of Technology, Kharagpur, from 27th April to 30th May 2015
  • Associate Co-ordinator, Saintgits Industrial Research Center (SIRC), inaugurated by Hon. Chief Minister of Kerala on 04th April 2013
  • IEEE Student Branch Counselor, Saintgits College of Engineering from June 2012 to March 2013
  • Setup of VLSI Design Lab for Post Graduation (PG) studies and Lab In-charge from 2012
  • Organizing member, International Conference on Global Innovations in Technology and Science (ICGITS) – 2012


  • First rank holder in M. Tech – VLSI Design with 8.95 CGPA, Kalasalingam University
  • Two years Higher Diploma Course in Software Engineering (HDSE) from 2001 – 2003
  • Six months Diploma Course on ” Embedded System” from CERD, College of Engineering, Guindy, Anna University.
  • Two days National workshop on “Design Entry for FPGA Implementation using VHDL ”, conducted at Vidya Mandhir Institute of Technology, Erode, Tamilnadu from 05th March 2015 to 06th March 2015
  • One and half month training program on “EDA Tool – Or CAD pSPICE & PCB Design”, conducted at Kalasalingam University from 24th Feb. 2009 to 04th Apr. 2009 

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