Er Jyothish Chandran G

Er Jyothish Chandran G
Er Jyothish Chandran G

Er Jyothish Chandran G

Designation : Asst Professor Sr
Education : M.Tech, Pursuing Ph.D
Professional Experience 
Teaching  : 17 yrs

Specialization :
UG : Electronics & Communication

PG : VLSI & Embedded System
Ph.D : VLSI Circuit design

Publication 

Journal Publications

  1. Implementation of an area efficient data converter with increased effective number of bits, –  Jan-2013, –  IEEE Xplore Digital Library
  2. 10 bit Delta Sigma D/A Converter with Increased S/N ratio Using Compact Adder Circuits –    Aug-2013, –  International Journal of Scientific & Engineering Research 
  3. Low leakage and high performance tag comparator implemented in 180nm CMOS technology    Feb-2015, –  Elsevier Procedia Computer Science
  4. Sub- 0.18μm Low Leakage and High Performance Dynamic Logic Wide Fan-in Gates, –  2015   IEEE Xplore Digital Library
  5. A Highly efficient carry select adder, – Oct-2015, – International Journal of Science Technology & Engineering(IJSTE)
  6. Design and Simulation of Binary Tree Comparators using Constant Delay Logic in 180nm Technology, – Oct-2015, – International Journal of Science Technology & Engineering(IJSTE) 
  7. Implementation of an efficient full adder Using Systematic Cell Design Methodology,- Jul-2016 –  International Journal of Scientific Development and Research (IJSDR)
  8. Pulse Triggered flip flop design with signal feed through scheme using conditional pulse enhancement technique, –  Aug-2016, -International Journal of Science Technology & Engineering(IJSTE)
  9. An efficient D flip flop using current mode signaling scheme, – Aug-2016 – International Journal of Science Technology & Engineering(IJSTE)
  10. Design and Analysis of an efficient full adder using Systematic Cell Design Methodology – Jan-17, –  ICTACT Journal of Microelectronics

Conference Publications 

  1. Detection of opens in latches using DFT in Mar-09, – NCACS at  SJCET Palai
  2. Watermarking of Digital Circuit Designs in Apr-09, – ICVCOM at Saintgits
  3. ZIGBEE Mesh Networking For a Swarm of Mobile Robots in Mar-2010, – NCETRSP FISAT Angamaly
  4. Behavioural Aspects of Interactive TV in Apr- 2011, – ICVCI at Saintgits
  5. Implementation of data converter with increased SNR and reduced number of transistors in Oct-2012, – National Conference on VLSI and Embedded Systems Technology and Advancements, VESTA2012, at Sreebudha College of Engineering
  6. Implementation of an area efficient data converter with increased effective number of bits in  Nov-2012, – 12th International Conf. on Intelligent System Design and Applications (ISDA) By MIR Lab at Cusat. Published in IEEE Explore
  7. 10 Bit Delta Sigma D/A Converter with Increased Signal to Noise Ratio Using Compact Adder circuits in Apr-2013, – International Conference on Global Innovations in Technology and Sciences (ICGITS- 2013) at SAINTGITS
  8. Sub- 0.18μm Low Leakage and High Performance Dynamic Logic Wide Fan-in Gates in  Jul-14, – International Conference on Magnetics, Machines & Drives (AICERA-2014 iCMMD) at Amal Jyothi College of Engineering, Kanjirapally
  9. Low leakage and high performance tag comparator implemented in 180 nm CMOS technology in Dec-2014, – International Conference on Information and Communication Technologies (ICICT 2014) at Cochin University of Science And Technology
  10. Design and Analysis of High Speed Low Voltage Clocked Double Tail Comparators,- Proceedings of 3rd Conference on Solid State Circuits, 2015 conducted by Saintgits 
  11. Design & Analysis of an efficient full adder using Systematic Cell Design Methodology in Aug-2016,- Proceedings of 4th Conference on Solid State Circuits, 2016 at Saintgits 
  12. Low Power Clock distribution network using Current mode clocked D flip flop with transmission gate in Aug-2016, – Proceedings of 4th Conference on Solid State Circuits, 2016 at Saintgits 
  13. Conditional pulse enhanced flip flop with signal feed through scheme in Aug-2016, –  Proceedings of 4th Conference on Solid State Circuits, 2016 at Saintgits 

Memberships

  • ISTE  Life Member

R & D Projects

  • Project “Dot Braille watch” is under development.

Research interest

  • VLSI Circuit design
  • Low power VLSI Circuits
  • Embedded system design
  • Renewable Energy Sources

Achievements

  • Project “Dot Braille watch” selected in the Finals of  “IDEA FEST 2018” conducted at  Marian Engineering College, Trivandrum on July 14th 2018, organized by Kerala Startup Mission, aimed for promoting the culture of innovation and entrepreneurship among the youth in the state of Kerala.
  • Project “Dot Braille watch” selected in the Finals under Contest Category in tekon (techfest of kscste) – 2018 held on 2nd February 2018.
  • Project Proposal Approved for funding by CERD on 24th October, 2016 – “Energy conservation by limiting elecrical energy wastage using effective detection of stationary and moving humans” r

Quick Contact

SAINTGITS COLLEGE OF ENGINEERING

Kottukulam Hills, Pathamuttom
PO Kottayam, Pin – 686532, Kerala

Tel: +91 481 2430349, 2436169, 2436170

Email: mail@saintgits.org

For Admission please contact:
Anju Anna Jacob
Admissions Officer
+91 9895903278, +91 8129702585
anjukakkad@saintgits.org

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