Er Sreekala K S

LATEST UPDATES

120 Students of Saintgits College of Engineering and 22 Students of Saintgits College of Applied Sciences placed in Infosys
Department of Corporate Economics will hold a National Seminar on “Economics Slowdown of India” in December 2019.
Congratulations Saintgits Chess Women’s Team – KTU C Zone Intercollegiate Chess Tournament Champions
Saintgits wins the prestigious IDA – STEM Award for Community Development.
National Seminar by Business Administration Department on the theme “Unleash Entrepreneurship in Trade & Commerce”  will be held on December 11, 2019.
Ms. Angel Baby and Ms. Gayathri R. from final year BCA of Saintgits College of Applied Sciences bagged the first placement offers in the new campus recruitment season. Both of them placed as Associate Analyst in Deloitte.
Er Sreekala K S
Er Sreekala K S

Er Sreekala K S

Designation : Asst Professor Sr
Education : M.Tech, Pursuing Ph.D
Professional Experience 
Teaching : 12.10 yrs

Research : 5 yrs

Specialization :
UG : Electronics & Communication
PG  : Digital Electronics
Ph.D : VLSI (Ph.D Pursuing)

 

Publication 

Journal

  • A paper entitled “State Retained Dual-Vth Feedback Sleeper-Stack  for Leakage Reduction” IET Computers and digital techniques 2018( Accepted)
  • A paper entitled “Leakage Estimation of SRAM cell based on Node Voltage and Current Characterization”, International Journal of Pure and Applied Mathematics, vol.118(7), Jan.2018,pp. 101-109
  • A paper entitled “FinFET based Ultra Low Power SRAM” International Journal of Engineering Research & Technology”, vol.7(04),April-2108, pp. 226-229
  • A paper entitled “Power and Read Delay Efficient Sensor based Compensation Technique for Low Power SRAM” Digital Library of Grenze Scientific Society, may 2018
  • A paper entitled ” RNM Calculation of 6T Sram Cell in 32nm Process Node based on Current and Voltage Information”Indian Journal of Science and Technology, Vol.10(29), Aug.2017,pp.1-7, DOI: 10.17485/ijst/2017/v10i29/116049
  • A paper entitled ” Environment and Target Simulator for Air Borne Radar ” is published in International Journal of Computer Applications – April 2011 .
  • A paper entitled ”   Modelling of on current in a Scaled MOSFET Considering the Effect of Saturation Velocity and Temperature ” is published in  International Journal of Scientific and Engineering Research – April 2013 .
  • A paper entitled ” Pattern and Position Dependent Gate Leakage and Reduction  Technique” is published in ICTACT journal of Microelectronics – October-2015
  • A paper entitled ”  Read stability analysis of 6T SRAM bit cell ” is published in IJRTER – May 2016.
  • A paper entitled ”  Read stability analysis of low voltage Schmitt trigger based SRAM ” is published in iiJrter – May-2016
  • A paper entitled ” Subthreshold Leakage Reduction by Feedback Sleeper-Stack ” is published in IEEE Xplorer as a part of IEEE International Conference on Emerging Technological Trends ” 2016
  • A paper entitled “Design and read stability analysis of 8t schmitt trigger based sram” is published in ICTACT journal of Microelectronics -January-2017

 Conference Proceedings

  • A paper entitled “Leakage Estimation of SRAM cell based on Node Voltage and Current Characterization”, Int. Conf. on Advances in Computer Science, Engineering and Technology, Krishnankoil, Thamil Nadu Jan. 2018
  • A paper entitled “Performance analysis of CMOS and FinFET based SRAM”, In. IEEE. Multi.Conf. on computing, communication, electrical and nanotechnology,Kottayam, Kerala, April 2018
  • A paper entitled “Compenstation Technique for LOW POWER SRAM – A Comparitive Study”, Nat. conf. on recent Trends in engg technology,  ,Pathanamthitta , Kerala, April 2017
  • A paper entitled “Design and read stability analysis of 8T Schmitt trigger based SRAM ” is published in Procedings in IEEE SSCS – , Kottayam, Kerala,2016 August
  • A paper entitled ”  Power efficient multiplier using PFAL Full adder ” is published in Procedings  in IEEE SSCS – 2016 August
  • A paper entitled ” Power and area efficient 10T SRAM with improved read stability ” is published in Procedings  in IEEE SSCS – 2016 August
  • A paper entitled ”  A paper entitled ”  Power and area efficient 10T SRAM with improved read stability ” is published in Procedings  of IEEE International Conference on Emerging Technological Trends at Baselios Mathews II College of Engineering, Kollam, 21st October, 2016
  • A paper entitled ”  A comparison analysis of low power high speed logic in 0.18um technology ” is published in Procedings  in ICRTETM -2014 at Mount Zion College of Engineering
  • A paper entitled ”  A comparison analysis of low power high speed logic in 0.18um technology ” is published in Procedings  in ICRTETM -2014 at Mount Zion College of Engineering
  • A paper entitled ”  Modelling of on current in a Scaled MOSFET Considering the Effect of Saturation Velocity and Temperature” is published in Procedings  in  International conference on global innovations in technology and sciences at Saintgits College of Engg  April 2013
  • A paper entitled ” Environment and Target Simulator for Air Borne Radar ” is published in Procedings  in  ICVCI-2011 at Saintgits College Of Engg
  • A paper entitled ” Water marking of Digital Circuit designs ” is published in Procedings  in  ICVCI 2009 at Saintgits College Of Engg
  • A paper entitled ” Pattern and Position Dependent Gate Leakage and Reduction  Technique ” is published in Procedings  in  IEEE SSCS at Saintgits College Of Engg-2015
  • A paper entitled “Adiabatic switching in the sub threshold region for low power ” is published in Procedings  in  IEEE SSCS at Saintgits College Of Engg-2015
  • A paper entitled ” Low Power High Speed Logic in Adder Circuit ” is published in Procedings  in  IEEE SSCS at Saintgits College Of Engg-2014
  • A paper entitled “Impact of Temperature and velocity Dependence On Drain current In MOSFET with Channel Scaling” is published in Procedings  in  National Conference in Communication ,control and Instrumentation  Engineering at FISAT, Angamaly -2012
  • A paper entitled ” Wi-Max Stability using Vanet ” is published in Procedings National Conference On Emerging Trends in RF and Signal Processing in FISAT,Angamaly – March 2010
  • A paper entitled ” AACM:Ad-Hoc Assisted Cellular Multicast ” NC-VCom(National Conference On VLSI and Communication at Saintgits College Of Engg.- March 2008

Participations

  • Participated 47th ISTE annual convention held at saintgits college of Engg. (27&28 January)
  • KSCSTE sponsored  Two day Workshop on ” Reserach methodology, Writing Practices, Language and Soft Skills” 18& 19 Jnauary 2018 at Saintgits College of Engg
  • KSCSTE sponsored FDP on Workshop on Role of VlSI& Embedded Systems in Next Generation Wireless Technologies , 28th Nov. to 3rd Dec. 2016 At Saintgits College Of Engg.
  • National workshop on Advanced Nano scale device design using TCAD  -28th December 2015 to 1st January 2016- Chenganoor Engg.College
  • Two day workshop on IC design flow using Mentor Graphics tool and Vivado design tool using zed board -26th June 2015 -Sreebuddha college of Engg,Patoor
  • IETE sponsored national Level faculty development programme on Embedded Design using ARM & ARDUINO- 18th-24th November 2015 – Saintgits College of Engg
  • National level  workshop on Signal processing in VLSI system Design- 28th to 30th September – Saintgits College of Engg
  • National level faculty development program on CAD tools in VLSI & Communication – 28th Nov-5th December 2014-Saintgits College of Engg
  • Two day ISTE e-Seminar on Step2 Research -20th sep 2014-Amal Jyothi College
  • National Level Faculty Development Programme On ’Orcad,Matlab and DSP Processor’- 2nd to 9th December-2013-Saintgits College Of Engg
  • ISTE workshop on”Creative Teaching”- 5th October-2013- Amal Jyothi College Of Engg
  • Workshop on” Research Methodology: Application of Research Methods and Statistics” 28th January to 1st February-2013- IUCDS,MG University
  • National Colloquium : Emerging areas of Research in Engineering Science”- 7-9 march 2013- RIT Pampady

  • Workshop on “Research Trends ,Tools Modelling and writing Skills”- 19-21 Aril 2012- Saintgits College of Engg
  • National workshop On “A-VIEW” – 14th December-2012- Amal Jyothi College Of Engg
  • ISTE workshop on ”Solar Photovoltaics: Fundamentals,Technologies and Applications”- 12th to 22nd December 2011- Amal Jyothi College Of Engg
  • Faculty Development Programme in “Digital Logic Design Using HDL” 21-22nd December 2010- Saintgits College of Engg
  • Training Programme on “Professional Excellence” -10th June-2009- ST.Joseph’s College Of Engg
  • Research Trends In Embedded systems and Signal Processing (Short term training Programme)- 28th October to 3rd November-2009-Saintgits College Of Engg
  • Faculty Development Programme in”ARM processors”- 4-5th January -2008- Saintgits College of Engg
  • Quality improvement programme on “Instructional Design and delivery”- 21st to 26th May 2007- SNGCE, Kadayirippu

Memberships

  • The Indian Society For Technical Education- Life member- LM-55264
  • The Institution Of Engg (INDIA)- Associate Member- A 533143-5

Research interest

  • Analog CMOS modelling
  • Digital CMOS modelling
  • CMOS VLSI
  • Low power VLSI
  • Memory

Achievements

  • GATE Score-  2003—–95.05%
  • Successfully Completed 12 weeks NPTEL course on VLSI Physical design  in 2017
  • Got Funding Rs. 40,000/- from KSCSTE to conduct workshop on Reserach methodology, Writing Practices, Language and Soft Skills
  • Co-investigator of KSCSTE funded( Rs.6,000)for student project entitled “Smart Driving System with Automatic Driver Alert and Braking Mechanism”. (2014-2018 batch)r

Quick Contact

SAINTGITS COLLEGE OF ENGINEERING

Kottukulam Hills, Pathamuttom
PO Kottayam, Pin – 686532, Kerala

Tel: +91 481 2430349, 2436169, 2436170

Email: mail@saintgits.org

For Admission please contact:
Anju Anna Jacob
Admissions Officer
+91 9895903278, +91 8129702585
anjukakkad@saintgits.org

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