Dr. Pradeep C

Designation: Professor
Education:  B.E, M.Tech, Ph.D.

Professional Experience
Teaching  : 20, Others: 2

Specialization
UG  : Electronics and Communication
PG  : VLSI Design

PhD: Information and Communication 

Publication  (latest come first in IEEE format)
International Journals

  1. Pradeep, C., Eapen, M.E., Joby, P.P. and Kizhakkethottam, J.J., 2018. Online placement and scheduling algorithm for reconfigurable cells in self-repairable field-programmable gate array systems. Computers & Electrical Engineering, 67, pp.836-850. Elsevier Publishing.
  2. Saranya, R., Pradeep, C. and Radhakrishnan, R., 2017. Design and implementation of a reconfigurable finite impulse response filter for adaptive systems. International Journal of Computational Systems Engineering, 3(1-2), pp.82-90. Inderscience Publishers.
  3. Nair, J.M. and Pradeep, C., 2016. Intelligent selective modular redundancy for online fault detection of adders in FPGA. International Journal of High Performance Systems Architecture, 6(4), pp.213-221. Inderscience Publishers.
  4. Varghese, Anila Ann, and C. Pradeep. “FPGA implementation of area-efficient single precision floating point complex divider with fault detection.” International Journal of Computational Systems Engineering 2.3 (2016): 174-181. Inderscience Publishers.
  5. Eapen, M.E., Pradeep, C., Varghese, A.A. and Nair, J.M., 2016. Placement Strategies for Faulty Cells in Module Relocation Based BISR Approach. Innovations in Bio-Inspired Computing and Applications (pp. 437-446). Springer International Publishing.
  6. Anjana, S., Pradeep, C. and Samuel, P., 2015. Synthesize of High Speed Floating-point Multipliers Based on Vedic Mathematics. Procedia Computer Science, 46, pp.1294-1302. Elsevier Publishing.
  7. Baby, N., Pradeep, C., Saranya, R. and Radhakrishnan, R., 2015. Synthesis of Reconfigurable Video Compression Modules in Virtex FPGAs for Multiple Fault Repair Mechanism. Procedia Computer Science, 46, pp.1333-1340. Elsevier Publishing.
  8. Saranya, R., Pradeep, C., Baby, N. and Radhakrishnan, R., 2015. FPGA Synthesis of Reconfigurable Modules for FIR Filter. International Journal of Reconfigurable and Embedded Systems (IJRES), 4(2).
  9. Pradeep, C, Radhakrishnan, R & Philip Samuel 2014, ‘Fault Recovery Algorithm Using King Spare Allocation and Shortest Path Shifting for Reconfigurable Systems’, Journal of Theoretical and Applied Information Technology, vol. 61, no.2, pp 254-261. 
  10. Pradeep, C, Radhakrishnan, R 2014, ‘FPGA Evaluation of Reconfigurable Modules with Self Repair Mechanism’, International Journal of Reconfigurable and Embedded Systems, vol.3, no.2,pp.1-12.
  11. Pradeep, C, Radhakrishnan, R, Saranya, R & Philip Samuel 2014, ‘Area Efficient Data Path with Online Fault Detection Mechanism for Reconfigurable Systems’, Australian Journal of Basic and Applied Sciences, vol.8, no.10, pp. 239-245.
  12. Pradeep, C, Radhakrishnan, R, Neena Baby & Philip Samuel, ‘Multi objective Built in Self Repair Algorithm with Multiple Fault Detection for Reconfigurable Systems’, Journal of Theoretical and Applied Information Technology, vol. 69, no.2,pp.248-256.
  13. Pradeep, C, Radhakrishnan, R 2014, ‘Fault Detection Methods for Interconnects of Reconfigurable Hardware’, I-manager’s Journal on Embedded systems, vol.4, no.2, pp.1-11.
  14. Pradeep C.”Design and Implementation of Reconfigurable LFSR “International Journal on Information and Communication Technologies, Volume 2, June 2009 (pp 139-142). 
  15. Reshma Mary John, Pradeep C., 2013 ”Self-Repairing Algorithm with Shared Spare Allocation for Reconfigurable Systems”, International Journal of Emerging Technology and Advanced Engineering. Volume 3, Issue 8, pp 716-721.
  16. Ajith Ravindran, Soya Treesa Jose and Pradeep C”A 1.5V Area Efficient Asynchronous Adder using MODL and Double Pass Transistor Logic” International Journal of Scientific & Engineering Research, Volume 4, Issue 8, August 2013

International and Conference

  1. Sai Usha Nagasri Goparaju, SVSLN Surya Suhas Vaddhiparthy, Pradeep C, Anuradha Vattem and Deepak Gangadharan,2021.Design of an IoT System for Machine Learning Calibrated TDS Measurement in Smart Campus.Presented in the 7th IEEE World Forum on Internet of Things (WF‑IoT).
  2. Baby, N. and Pradeep, C., 2014, July. FPGA partitioning and synthesis of reconfigurable video compression module. In Control, Instrumentation, Communication and Computational Technologies (ICCICCT), 2014 International Conference on (pp. 360-364). IEEE Xplore.
  3. Saranya, R. and Pradeep, C., 2014, July. FPGA synthesis of area efficient data path for reconfigurable FIR filter. In Control, Instrumentation, Communication and Computational Technologies (ICCICCT), 2014 International Conference on (pp. 349-354). IEEE Xplore.
  4. Anjana, S. and Pradeep, C., 2014, July. High speed integer multiplier designs for reconfigurable systems. In Control, Instrumentation, Communication and Computational Technologies (ICCICCT), 2014 International Conference on (pp. 393-397). IEEE Xplore.
  5. Pradeep, C, Radhakrishnan, R & Philip Samuel 2014, ‘Reduced Time Testing Method for Permanent Faults in Interconnects of Reconfigurable Hardware’, Proceedings of International Conference On Systemic, Cybernetics and Informatics, vol. 1 & 2, pp. 018-022.
  6. Pradeep C,”Design and Implementation of 32 bit RISC Processor in FPGA” Proceedings of National Conference NCACS 2009, SJCET, Pala, Kottayam. pp 5-10.
  7. Pradeep C, “Verilog HDL implementation of Superscalar Processor with Speculative branch Prediction”, Proceedings of National Conference NC-(ET) 2, SAINTGITS College of Engineering, Kottayam. pp 315-318.
  8. Pradeep C, NIMISHA SUBHASH, RESHMA MARY JOHN, 2013.” Permanent Fault Detection Method for Interconnects in Reconfigurable Systems”, Proceedings of U.G.C Sponsored III National Conference on Modern Trends in Electronic Communication & Signal Processing.
  9. Reshma Mary John, Pradeep C., 2013. ”Responsive Back-Up Circuits (RBC) Inspired Fault-Recovery Algorithm for Reconfigurable Systems”, Proceedings of U.G.C Sponsored III National Conference on Modern Trends in Electronic Communication & Signal Processing.
  10. Ajith Ravindran, Soya Treesa Jose and Pradeep C “A 1.5V Area Efficient Asynchronous Adder using MODL and Double Pass Transistor Logic”  Proceedings of International Conference on Global Innovation in Technology and Sciences (ICGITS 2013),4-6th April 2013.
  11. Jose, S.T. And Pradeep, C,2013 “Design of a multichannel NAND Flash memory controller for efficient utilization of bandwidth in SSD’s “proceedings of International Multi-Conference on Automation, Computing, Communication, Control and Compressed Sensing (iMac4s), 22-23 Mach 2013, Kottayam,India.pp 235 – 239. IEEE Xplore.
  12. Oommen,D. and Pradeep,C.,2012 “Reconfigurable router using RLBS algorithm ” Proceedings of 12th International Conference on Intelligent Systems Design and Applications (ISDA). 27-29 Nov.2012, Kochi, India. pp 332 – 336. IEEE Xplore
  13. Aith Ravindran And Pradeep C.,2012″1.5v, .18u Area Efficient 32 Bit Adder using 4T XOR and Modified Manchester Carry Chain ” Proceedings of 12th International Conference on Trends in Innovative Computing 2012 – Intelligent Systems Design, 27-29 Nov.2012, Kochi,India.pp 140 – 144.
  14. Aith Ravindran and Pradeep C “Area Efficient Quad Bit PTL Adder”, In Proc. of National Conference on VLSI and Embedded Systems Technology and Advancements, VESTA2012, Pg. 194 – 198, Oct. 2012. 
  15. Soya Treesa Jose and Pradeep C, “Design of High Performance Flash Memory Controller,” In Proc. of National Conference on VLSI and Embedded Systems Technology and Advancements, VESTA2012, Pg. 28 – 31, Oct. 2012.
  16. Dhanya Oommen and Pradeep C,”RLBSA-Adaptive Routing Algorithm for NOC,” In Proc. of National Conference on VLSI and Embedded Systems Technology and Advancements, VESTA2012, Pg. 60 – 64, Oct. 2012. 
  17. Mathew, B.K., John, S.K., Pradeep, C., 2008 “New Technique for Fault Detection in Quantum Cellular Automata “Proceedings of First International Conference on Emerging Trends in Engineering and Technology (ICETET ’08),16-18 July 2008, Nagpur, Maharashtra, India. pp 834 – 837. IEEE Xplore.
  18. Binu K Mathw, Pradeep C and Shajimon K John, “DFT Techniques for opens in CMOS latches” Proceedings of First International Conference on Advances in Computing, Chikhli, India, 21-22 February 2008. 

Participations

Workshop/Seminars Attended

  1. Successfully completed the Short Term Training Programme on Scientic Computing with Python from 9th to 20th November 2020, organised by the Department of Electronics & Communication Engineering and sponsored by the Technical Education Quality Improvement Programme (TEQIP), Govt. of India.
  2. One day Workshop on ‘Innovation-led and Technology-Intensive Entrepreneurship: The Way Ahead for Kerala’’ Kerala financial Corporation, Kerala.3rd Dec. 2013.
  3. One day ISTE e-Workshop on  ‘Creative Teaching’’ organized by ISTE Kerala Session & Amaljyothi College of Engineering ,Kanjirapally, Kottayam, Kerala.5th Oct 2013.
  4. Two day workshop on ‘Patents’ organized by AmalJyothi College of Engineering from 27th  – 28th  Sept, 2013.
  5. Two weeks ISTE workshop on ‘Software Development  Techniques for Teachers of Engineering and Science Institutes’ Conducted by IIT Bombay under National Mission through ICT.5th Nov-5th Nov,2011.
  6. Three day International conference on ‘Emerging Research Areas’ at Amaljyothi College of Engineering ,Kanjirapally, Kottayam, Kerala.28th -30th April,2011.
  7. Twelve Day National Faculty Development Program ‘Entrepreneurship’ organized by  Entrepreneurship Development Institute of India and  Technopark Trivandrum .Oct 19th -30th, 2010.
  8. Two day Short Term Course on ‘methodology and Software for Research’ conducted at  SAINTGITS College of Engineering , Kottayam ,Kerala.17th-18th Dec,2010.
  9. Two day National Workshop on ‘Opportunities of Government Funded R&D Projects for Academic Institutions’, Conducted at Toc H Institute of Science and Technology.06-07 Nov 2009.  
  10. Eight day STTP program on ‘Research Trends in Embedded Systems and Signal Processing’, By ISTE Kerala Section at SAINTGITS College of Engineering , Kottayam , Kerala.28th Oct-3rd Nov 2009.
  11. Seven day Faculty Development Program on ‘Neo Areas of Research in Computing’ organized by  ISTE Kerala Section and Dept. of CSE  Amaljyothi College of Engineering, Kanjirapally, Kottayam, Kerala. 26th Nov-2nd Dec,2008.
  12. One day seminar  on ‘Demystifying Wavelets’ conducted at SJCET ,Choodacherry, Palai, Kerala.28th March, 2008.
  13. Eight day Short term tainting program on ‘Evolving Trends In Electronics And Communication’ Sponsored By ISTE Kerala Section at Amaljyothi College of Engineering ,Kanjirapally, Kottayam, Kerala.7th -14th Jan,2008.
  14. Two day Faculty Development Program on ARM Processors conducted at SAINTGITS College of Engineering, Kottayam ,Kerala.4th-5th Jan 2008.
  15. One day seminar on Image Processing And Research Methodologies conducted at SAINTGITS College of Engineering, Kottayam ,Kerala.14th Aug,2007.
  16. Two day Symposium on TI DSP by Cranes Software International Limited, Bangalore conducted at SJCET, Choodacheri, Palai, and Kerala.14th -16th Jan 2006. 

As resource Person

  1. Delivered a talk on  “Artificial Intelligence-powered loT” as part of  AICTE – ISTE Sponsored Workshop on “Internet of Things (IoT) using Arduino and Raspberry Pi-Phase I” from 09.02.2021 to 15.02.2021 organized by GRG Polytechnic College, Coimbatore.
  2. Served as one of the external expert members for NBA peer team mock visit organized by Centre of Academic Excellence of NSRIT Visakh during March 2-3 , 2022 for the program Electronics and Communication Engineering.

Events Organized

  1. Chief Co-ordinator of National Level Project Exhibition and Competition SRISHTI 2015 at SAINTGITS College of Engineering.
  2. Co-ordinator of AICTE-sponsored Project Exhibition and Competition SRISHTI 2014 at SAINTGITS College of Engineering.
  3. Organizing Secretary of International Conference ICGITS 2013 at SAINTGITS College of Engineering.
  4. Program Chair of International Conference ICVCI 2011 at SAINTGITS College of Engineering.
  5. Co-ordinator of International Conference IC“VCom 2009 at SAINTGITS College of Engineering.
  6. Co-ordinator of National Conference NC“VCom 2008 at SAINTGITS College of Engineering. 
  7. Convener of Transportation   Committee of National Conference NC-(ET )2 , 2007 at SAINTGITS College of Engineering. 
  8. Organizing Committee Member of National Conference NC“VCom 2007 at SAINTGITS College of Engineering. 
  9. Co-ordinator for Faculty Development Program on ARM Processors at SAINTGITS College of Engineering.

Membership

1 IE(I)- Fellow

2 IETE – Fellow

3 IEEE – Senior Member

4 IAENG – Member

5 ISTE – Life Member

Research Interest

  • VLSI 
  • AI-IoT 
  • Intelligent Transportation for Smart Cities in India 
  • FPGA-based System Design

R & D Projects

Role : Co‑Principal Investigator

Project : Design, development, and deployment of energy‑efficient smart EDGE        devices for real‑time traffic flow prediction and control

Amount : INR. 40 lakhs

Period : 3 Years (2021‑2023)

Agency : DST (Government of India), NMICPS, TiHAN at IIT Hyderabad (https://tihan.iith.ac.in/)

PI’s : Dr. Balaji Raman , IIIT, Sri City, Chittoor & Dr. Deepak Gangadharan, IIIT, Hyderabad

Co‑PI’s : Dr. Piyush Joshi  , IIIT, Sri City.

Achievement

  1. Approved Research supervisor of APJ Abdul Kalam Technological University, Thiruvananthapuram, Kerala from 2018.
  2. Reviewer of Inderscience Journals

Contact Details

Phone: 9447661355

Email: pradeep.c@saintgits.org

Website:Linkedin:https://www.linkedin.com/in/dr-pradeep-chandrasekhar-33641932