Er. Hanna Mathew

Designation: Assistant Professor -Senior. Grade
Education:  B.Tech, M.E, Ph.D(Doing)

Professional Experience
Teaching  : 12  years

UG  : in Electronics and Communication
PG  : ME in Applied Electronics

PhD: VLSI Signal Processing

Publication  (latest come first in IEEE format)
International Journals

  1. Published a paper titled  “The Novel Intravenous Fluid Level Indicator for Smart IV Systems”  in the  “International Research Journal of Engineering and Technology , Issue 6, June 2020.
  2. Published a paper titled “CRC Checking for high speed LFSR with modified state space transformation model” in the International Journal of Electrical, Electronics and Data Communication, ISSN 2321-2950, Volume 7, Issue 9, September 2019
  3.  Published  a paper titled  “Dual mode CMOS ISFET Sensor for DNA Sequencing” in IEEE Xplorer on 23rd April, 2018.

International Conference

  1. Presented the paper “CMOS DNA Sequencing Arrays- A Gateway to Advanced DNA Computing” in the International Conference on Wireless Communications Signal Processing and Networking(WiSPNET2017) at  SSN College of Engineering, Chennai on March 2017
  2.  Presented the paper “A Review on Research and Advancements in LoC Doping-less Germanium Tunnel FET” in the IEEE SSCS Sponsored Conference on Solid State Circuits Proceeding of IEEE SSCS Chapter at SAINTGITS College of Engineering, Kottayam on August 2015
  3. Presented the paper “A Low Power Memory Design Using Clock Gating Technique in ICVCI-11 at SAINTGITS College of Engineering, Kottayam on April 2011
  4. Presented the paper “A novel delay buffer for low power applications in ICSO-10 at Karpagam College of Engineering February 2010


Workshop/Seminars Attended

  1.  NPTEL Online certification (FDP) on the course VLSI Signal Processing from February 2022 to April  2022 conducted by IIT Kharagpur.
  2. 4 weeks  online Lab Workshop on ‘FPGA Architecture and Programming using Verilog HDL’ jointly organized by Arm Education and NIELIT Calicut from  4thApril 2022 to 30th April 2022.      
  3.  FDP on Advancements in Signal Processing and Optimization techniques in WSN   from 21/09/20 to 25/09/20 organized by  Poornima  College of Engineering, Jaipur.  
  4. Online course on “IMAGE PROCESSING USING VLSI ARCHITECTURES” at  IIT Roorkee from  17th to 21st December, 2020. 
  5. FDP on Emerging Research Trends in VLSI, MEMS and Signal Processing from 10/08/20 to 13/08/20 at SAINTGITS College of Engineering.
  6.  NPTEL Online certification (FDP) on the course ” Switching Circuits and Logic Design”  from July 2019-october 2019 conducted by  IIT Madras.               
  7. NPTEL Online certification (FDP) on the course Principles of Signals and System  from January  2019-April 2019 conducted by IIT Kanpur.                  
  8. FDP on Mathematical Foundations for Communication Engineering  from 07/01/19  to 11/01/19 at TKM College of Engineering.
  9. One day workshop on mentoring SAINTGITS College of Engineering, 15/09/ 2018.
  10. FDP on Antennas and RF Devices” from 11/06/18 to 16/06/18 at SAINTGITS College of Engineering.
  11. Workshop on “Research Methodology, Writing Practices, Language & Soft Skills from 18/01/18 to 19/01/18 at SAINTGITS College of Engineering.
  12. CMOS, Mixed Signal and Radio Frequency VLSI Design by IIT Kharagpur at SAINTGITS from 30/01/17 to 04/02/17 .
  13. Workshop for Women in Science & Engineering(WiSE) at Indian Institute of Science  Bangalore.
  14. Role of VLSI & Embedded Systems in Next Generation Wireless Technologies from 28/11/16  to  03/12/16  at SAINTGITS College of Engineering .
  15.   National level FDP on Embedded design using ARM & ARDUINO at SAINTGITS College of Engineering from 18/11/2015 to 24/11/2015.
  16.  Workshop on Signal processing in VLSI system design at SAINTGITS College of Engineering from 28/09/2015 to 30/09/2015. 

Events Organized

  1. Organized a webinar on  the topic  “Women’s health with special reference to PCOS”  on 28/09/20


  •  Member-IEEE [ Membership no: 98336114 ].
  • ISTE Life Member

Research Interest

  • VLSI Design
  • VLSI Signal Processing

R & D Projects

CERD 2020-21 students project fund(Co –Investigator) for an amount of Rs:13547/.                        

Contact Details